1. Field of the Invention
The present invention relates to a semiconductor memory device, and its test method as well as a test circuit integrated in the semiconductor memory device.
2. Prior Art
It is necessary for the semiconductor memory device to make a variety of test before shipment, for which purpose in may cases, a test circuit has previously been provided in the semiconductor memory device.
FIG. 1 is a block diagram of a semiconductor memory device with such a test circuit, for example, one structural example of a pseudo SRAM (a pseudo static random access memory). The structure of this conventional semiconductor memory device is disclosed in Japanese Laid-open Patent Publication No. 1-125796. This semiconductor memory device has the following structure.
A memory array 1 has a plurality of memory cells which store data. A sense amplifier 2 is connected to the memory cell array 1 for amplifying data from the memory array 1. A column I/O circuit 3 becomes connected to a bit line of the memory cells in the memory array 1 for selectively activating this bit line. A column decoder 4 receives an input of external addresses A8–A15 and is connected to the column I/O circuit 3, so that the external addresses A8–A15 enter into the column I/O circuit 3, whereby the column I/O circuit 3 selectively activates a bit line based on these external addresses A8–A15. Further, a main amplifier/write buffer 5 is provided for writing or reading data
A multiplexer 8 is connected to an output side of a refresh control circuit 12 and also connected to an output side of an address counter 9, so that in accordance with an output signal from a refresh control circuit 12, the multiplexer 8 selects any of externally entered external addresses A0–A7 and the refresh address outputted from the address counter 9. An output side of the multiplexer 8 is connected to a row decoder 7 so that selected one of the external addresses A0–A7 or the refresh address is inputted into the row decoder 7. The row decoder 7 is connected to a word driver 6 so that any one of the external addresses A0–A7 or the refresh address is inputted into the word driver 6. The word driver 6 is connected to a word line of the memory cell in the memory array 1, so that the word driver 6 selectively activates the word line based on the external addresses A0–A7 or the refresh address.
A test mode deciding circuit 10 receives an input of a /CE signal (/ representing a negative logic signal) or a /RFSH signal, so that the test mode deciding circuit 10 decides whether the mode is a test mode or not, and outputs a test signal which indicates the decided result. An output control circuit 14 is connected to an output side of the test mode deciding circuit 10, so that the output control circuit 14 is controlled by the test signal outputted from the test mode deciding circuit 1 and outputs an I/O output switching signal. Further, the output control circuit 14 is connected to the timer circuit 11 and the I/O output switching circuit 15, so that for test, the output control circuit 14 controls the I/O output switching circuit 15, whereby a frequency divided signal outputted from the timer circuit 11 is supplied through the I/O output switching circuit 15 to an I/O terminal.
The refresh control circuit 12 receives inputs of the /CE signal and the /RFSH signal, so that if those signals satisfy predetermined conditions, then the refresh control circuit 12 performs refresh operations of the memory cells. The above-described timer circuit 11 outputs a refresh request signal periodically at a constant time interval. The timer circuit 11 is connected to the refresh control circuit 12 so that the refresh request signal is inputted into the refresh control circuit 12. A timing generating circuit 13 is connected to this refresh control circuit 12 for receiving an input of the refresh control signal outputted from the refresh control circuit 12 and also receives external inputs of an /RE signal, an /OE signal and a CS signal, so that the timing generating circuit 13 outputs an internal synchronizing signal and controls operations of the entirety of the circuit.
In such configurations, if the /RFSH signal is a low level (L) at a time when the /CE signal is transited from a high level (H) to a low level (L), then the test mode deciding circuit 10 decides that the mode is the test mode. In this case, the test mode deciding circuit 10 transmits a signal through the output control circuit 14 and outputs this signal for oscillating the timer circuit 11, whereby the refresh control circuit 12 operates the address counter 9 and controls the multiplexer 8, so that the refresh address (n-address) of the address counter 9 is outputted from the multiplexer 8 as the row address of the memory cells. The external addresses A8˜A15 are entered as the column addresses to the column decoder 4.
In the above manners, a memory cell of a designated address by the row address of n-address and the column addresses A8˜A15, so that a read out operation of data content of the cell is accomplished. Accordingly, the specific data have previously been written into the cell of this address so that in the test mode, the content in the cell is directly read out, thereby accurately deciding whether or not data have correctly been written and read out. Namely, it is possible to accurately decide whether or not the timer circuit 11 and the address counter 9 normally operate.
When the mode is set into the test mode, the timer circuit 11 is oscillated, wherein the frequency divided signal outputted from the timer 11 is supplied through the output switching circuit 15 to the I/O7 terminal. Checking the frequency divided output signal results in an accurate decision on whether or the timer circuit 11 normally operates.
Issue to be Solved by the Invention
The above described pseudo SRAM is a semiconductor memory device which has the same memory cell structure as the DRAM (dynamic random access memory), and has the same condition in use as the SRAM, wherein it is necessary to internally perform a self-refresh of the memory cells every when a predetermined time passes.
The address of the memory cell to be self-refreshed or the refresh address is generated by the inside of the circuit, for which reason the refresh address is completely irrelevant to the externally suppleid read/write addresses.
In the worst case, for example, it is possible that adjacent two of the word lines are sequentially activated, wherein the common bit line is activated. In this case, it is possible that any memory malfunction appears due to an insufficient pre-charge and a slight leakage of current under a field insulating film.
The test conducted by the above-described semiconductor memory device is, however, only to check the operations of the timer circuit 11 and also sequentially read out the data of the memory cells by sequentially changing the counted value of the address counter 9. It is impossible to intentionally check the operations or make the test in the worst case which is likely to cause the above-described malfunction.
In consideration of the above-described circumstances, an object of the present invention is to provide a semiconductor memory device which is capable of checking operations under any conditions.
A further object of the present invention is to provide a test circuit integrated in a semiconductor memory device and capable of checking operations under any conditions.
A furthermore object of the present invention is to provide a test method capable of checking operations a semiconductor memory device under any conditions.
Means for Solving the Issue
The present invention was made to solve the above-issues, and provides a test method for a semiconductor memory device with a plurality of memory cells which need refreshes, wherein during a test operation, there is accomplished, at least one time, a combination of: a read/write process for reading or writing the memory cell based on a first address externally entered; and a refresh process for refreshing the memory cells based on a second address externally entered.
The combination of two processes may optionally be that after the refresh process is made, then the read/write process is made.
The combination of two processes may optionally be that after the read/write process is made, then the refresh process is made.
The combination of two processes may optionally be made in one cycle.
The read/write process and subsequent the refresh process and further subsequent the read/write process may optionally be accomplished in one cycle.
The two processes may optionally be made at a common column address and at row addresses close to each other.
The two processes may optionally be made at a common column address and at row addresses adjacent to each other.
The test method for a semiconductor memory device may optionally further include a process of discontinuing the refresh of the memory cell based on a third address generated inside of the semiconductor memory device, in response to a switch of the semiconductor memory device from a normal operation mode to a test mode.
When the normal operation mode is switched to the test mode based on a mode switching signal externally entered, the test address may be selected from the third address and the test address, so that the refresh of the memory cell based on the third address may be discontinued.
The semiconductor memory device may optionally be switched from the normal operation mode to the test mode based on a mode switching signal externally entered.
When the normal operation mode may be switched to the test mode based on the mode switching signal externally entered, the test address may be selected from the third address and the test address, so that the refresh of the memory cell based on the third address may be discontinued.
The test operation may optionally be that a set of plural row addresses is subject to the refresh operation with fixing a column address and sequentially changing row addresses.
The test operation may optionally be that a set of all row addresses is subject to the refresh operation with fixing a column address and sequentially changing row addresses.
The test operation may optionally be that a set of respective all row addresses for each of plural blocks divided from a memory cell array is subject to the refresh operation with fixing a column address and sequentially changing row addresses.
Both the first address and the second address may optionally be externally entered every changes of the row address.
The first address may optionally be externally entered every changes of the row address, while only an initial address of the second address is externally entered, and the second address may be automatically changed in accordance with a predetermined constant rule every changes to the row address.
A predetermined increment of the second address may optionally be made every changes to the row address.
A hold test of a memory cell to be subject to the test may be previously tested and a predetermined test pattern may be written, before the two processes may be accomplished.
The present invention provides a semiconductor memory device having a plurality of memory cells which need refresh, a circuit element for supplying a first address, and an access address control circuit for refreshing the memory cell based on an address, wherein the semiconductor memory device further has: a circuit for holding a second address externally entered; and a refresh address switching circuit electrically coupled to the circuit element for supplying the first address and also coupled to the circuit for holding the second address, and in a normal operation mode, the refresh address switching circuit supplies the first address to the access address control circuit, and in a test mode, the refresh address switching circuit supplies the second address to the access address control circuit.
The refresh address switching circuit may optionally comprise a selecting circuit which is electrically coupled to the circuit element for supplying the first address and also coupled to the circuit for holding data, and in the normal operation mode, the selecting circuit selects the first address, and in the test mode, the selecting circuit selects the second address.
The selecting circuit may optionally comprise a multiplexer electrically coupled to the circuit element for supplying the first address and also coupled to the circuit for holding data.
The semiconductor memory device may optionally further include: a control circuit electrically coupled to the refresh address switching circuit for supplying the refresh address switching circuit a control signal which switches between the normal operation mode and the test mode.
The control circuit may optionally comprise a test entry circuit which switches between the normal operation mode and the test mode in response to a predetermined external signal.
The circuit for holding the second address may optionally comprise a data storage device electrically coupled to the refresh address switching circuit.
The semiconductor memory device may optionally further include an address inverting circuit electrically coupled to between the circuit for holding data and the refresh address switching circuit for inverting the second address outputted from the data storage device, and supplying the same to the refresh address switching circuit.
The circuit element for supplying the first address may optionally comprise a refresh address generating circuit connected to the refresh address switching circuit.
The present invention provides a test circuit for a semiconductor memory device, the circuit having a plurality of memory cells which need refresh and a circuit element for supplying a first address based on an internal signal, wherein the test circuit has: a circuit for holding a second address externally entered; and a refresh address switching circuit electrically coupled to the circuit element for supplying the first address and also coupled to the circuit for holding the second address, and in a normal operation mode, the test circuit supplies the first address to the access address control circuit, and in a test mode, the test circuit supplies the second address to the access address control circuit.
The refresh address switching circuit may optionally comprise a selecting circuit which is electrically coupled to the circuit element for supplying the first address and also coupled to the circuit for holding data, and in the normal operation mode, the selecting circuit selects the first address, and in the test mode, the selecting circuit selects the second address.
The selecting circuit may optionally comprise a multiplexer electrically coupled to the circuit element for supplying the first address and also coupled to the circuit for holding data.
The test circuit may optionally further include: a control circuit electrically coupled to the refresh address switching circuit for supplying the refresh address switching circuit a control signal which switches between the normal operation mode and the test mode.
The control circuit may optionally comprise a test entry circuit which switches between the normal operation mode and the test mode in response to a predetermined external signal.
The circuit for holding the second address may optionally comprise a data storage device electrically coupled to the refresh address switching circuit.
The test circuit may optionally further include an address inverting circuit electrically coupled to between the circuit for holding data and the refresh address switching circuit for inverting the second address outputted from the data storage device, and supplying the same to the refresh address switching circuit.
The test circuit may optionally be integrated in the semiconductor memory device, or be separated from the semiconductor memory device and be mounted on a same chip as the semiconductor memory device. In either configuration, there is no problem, provided that the test circuit is electrically coupled to the semiconductor memory device, and signals and addresses are transmitted between the test circuit and the semiconductor memory device.